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CUSTOMER PROCUREMENT SPECIFICATION
Z86C90/C89
ROMLESS CMOS Z8(R) 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The Z86C90/C89 CCPTM (Consumer Controller Processor) introduces a new level of sophistication to single-chip architecture. The Z86C90/C89 are ROMless members of the Z8 single-chip microcontroller family with 236 bytes of general purpose RAM. The only difference that exists between the Z86C89 and the Z86C90 is that the on-chip oscillator of the Z86C89 can accept an external RC network or other external clock source, while the Z86C90's on-chip oscillator accepts a crystal, ceramic resonator, LC, or external clock source drive. The CCP controllers are housed in a 40-pin DIP, 44-pin Leaded Chip Carrier, or a 44-pin Quad Flat Pack, and are CMOS compatible. The CCP offers the use of external memory which enables this Z8 microcomputer to be used where code flexibility is required. Zilog's CMOS microcomputer offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The Z86C90/C89 architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow access to register mapped peripheral and I/O circuits. The CCP offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many industrial, automotive, computer peripherals, and advanced scientific applications. The CCP applications demand powerful I/O capabilities. The Z86C90/C89 fulfills this with 32 pins dedicated to input and output. These lines are grouped into four ports. Each port consists of eight lines, and is configurable under software control to provide timing, status signals, parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are four basic address spaces available to support this wide range of configurations: Program Memory, Register File, Data Memory, and Expanded Register File. The Register File is composed of 236 bytes of general purpose registers, four I/O port registers, and fifteen control and status registers. The Expanded Register File consists of two control registers. To unburden the program from coping with the real-time problems, such as counting/timing and data communication, the Z86C90/C89 offers two on-chip counter/timers. Included are a large number of user selectable modes, and two on-board comparators to process analog signals with a common reference voltage (see Functional Block Diagram).
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
DC-4054-01
(10-17-91)
1
GENERAL DESCRIPTION (Continued)
Output Input Vcc GND XTAL /AS /DS R//W /RESET
Port 3
Machine Timing & Instruction Control RESET WDT, POR
Counter/ Timers (2)
ALU
FLAGS Interrupt Control Register Pointer Register File 256 x 8-Bit Program Counter
Two Analog Comparators
Port 2
Port 0
Port 1
4 I/O (Bit Programmable)
4
8 Address/Data or I/O (Byte Programmable)
Address or I/O (Nibble Programmable)
Functional Block Diagram
2
PIN DESCRIPTION
R//W P25 P26 P27 P04 P05 P06 P14 P15 P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 /DS P24 P23 P22 P21 P20 P03 P13 P12 GND P02 P11 P10 P01 P00 P30 P36 P37 P35 /RESET
32 Z86C90/C89 31 10 DIP 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21
40-Pin DIP Pin Assignments
3
PIN DESCRIPTION (Continued)
GND GND P20 P03 P13 P12 P02 P11 P10 P01 P00
39 38 37 36
6 P21 P22 P23 P24 /DS N/C R//W P25 P26 P27 P04 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 P30 P36 P37 P35 /RESET GND /AS P34 P33 P32 P31
Z86C90/C89 PLCC
35 34 33 32 31 30 29
18 19 20 21 22 23 24 25 26 27 28
44-Pin PLCC Pin Assignments
GND GND P20 P03 P13 P12 P02 P11 P10 P01 P00
33 32 31 30 29 28 27 26 25 24 23 P21 P22 P23 P24 /DS N/C R//W P25 P26 P27 P04 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 P30 P36 P37 P35 /RESET GND /AS P34 P33 P32 P31
Z86C90/C89 QFP
XTAL2
P05
P06
P14
P15
P07
P16
P17
44-Pin QFP Pin Assignments
4
XTAL1
VCC
VCC
XTAL2 XTAL1
18 17 16 15 14 13 12
P05
P06
P14
P15
P07
P16
VCC
VCC
P17
STANDARD TEST CONDITIONS
+5V
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram).
2.1 K
From Output Under Test
150 pF 9.1 K
Test Load Diagram
ABSOLUTE MAXIMUM RATINGS
Symbol VCC T STG TA Description Supply Voltage (*) Storage Temp Oper Ambient Temp Power Dissipation Min -0.3 -65 Max +7.0 +150 2.2 Units V C C W ings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an e x t e n d e d period may affect device reliability.
Notes: on all pins with respect to GND. * Voltage See Ordering Information.
Stress greater than those listed under Absolute Maximum Rat-
CAPACITANCE
T A = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins to GND Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF
PLEASE NOTE
These devices will not operate in extended timing mode. Set Register 248, D5 = 0.
5
DC CHARACTERISTICS
Sym Notes Parameter VCC Note [3] Max Input Voltage VCH Clock Input High Voltage 3.3V 5.0V 3.3V 5.0V VCL Clock Input Low Voltage 3.3V 5.0V VIH VIL VOH VOL1 VOL2 Input High Voltage Input Low Voltage Output High Voltge Output Low Voltage Output Low Voltage 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V VRH VRl VOFFSET IIL IOL IIR ICC [4,5] [4,5] 3.3V 15 15 5 mA @ 12 MHz Reset Input High Voltage Reset Input Low Voltage Comparator Input Offset Voltage Input Leakage Output Leakage Reset Input Current Supply Current 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V T A = 0C to 70C Min Max 7 7 VCC+0.3 VCC+0.3 TA = -40 C to 105 C Min Max 7 7 VCC+0.3 VCC+0.3 Typ @ Units 25C V V V V V V V V V V V V V V V V V V IOH = -2.0 mA IOH = -2.0 mA IOH = +4.0 mA IOL = +4.0 mA IOL = +6 mA, 3 Pin Max IOL = +12 mA, 3 Pin Max IIN 250A IIN 250A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Conditions
0.7 VCC 0.7 VCC
0.7 VCC 0.7 VCC
1.3 2.5 0.7 1.5 1.3 2.5 0.7 1.5 3.1 4.8 0.2 0.1 0.3 0.3 1.5 2.1 1.1 1.7 10 10 <1 <1 <1 <1 -20 -30 4 10
GND -0.30.2 VCC GND-0.3 0.2 VCC 0.7 VCC VCC+0.3 0.7 VCC VCC+0.3 GND-0.3 0.2 VCC GND-0.3 0.2 VCC VCC-0.4 VCC-0.4 0.6 0.4 1.2 1.2 .8 VCC VCC .8 VCC VCC GND-0.3 0.2 VCC GND-0.3 0.2 VCC 25 25 -1 -1 -1 -1 1 1 1 1 -45 -55 10 15
GND-0.3 0.2 VCC GND-0.3 0.2 VCC 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC-0.4 0.6 0.4 1.2 1.2 .8 VCC .8 VCC GND-0.3 GND-0.3 VCC VCC 0.2 VCC 0.2 VCC 25 25 2 2 2 2 -60 -70 10 15 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
mV mV A A A A A A mA mA VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
-1 -1 -1 -1
@ 8 MHz @ 8 MHz
6
[4,5] 5.0V [4,5] 20 20 15 mA @ 12 MHz
Sym Notes
Parameter
VCC Note [3]
T A = 0C to 70C Min Max 3
T A = -40 C Min
Typ @ Units
Conditions
to 105 C 25C Max 3 1 mA HALT Mode VIN = OV, VCC @ 8 MHz HALT Mode VIN = OV, VCC @ 8 MHz HALT Mode VIN = OV, VCC @ 12 MHz HALT Mode VIN = OV, VCC @ 12 MHz
ICC1 [4,5]
Standby Current
3.3V
5.0V [4,5]
5
5
2.4
mA
3.3V [4,5]
4
4
1.5
mA
5.0V [4,5]
6
6
3.2
mA
3.3V [4,5] 5.0V [4,5] 3.3V [4,5] 5.0V [4,5]
2
2
0.8
mA
Clock Divide by 16 @ 8 MHz Clock Divide by 16 @ 8 MHz Clock Divide by 16 @ 12 MHz Clock Divide by 16 @ 12 MHz
4
4
1.8
mA
3
3
1.2
mA
5
5
2.5
mA
ICC2
Standby Current
3.3V
8
15
1
A A A
5.0V
10
20
2
3.3V OV, V CC
500 V IN =
600
310
STOP Mode [6] VIN = OV, VCC WDT is not Running STOP Mode [6] VIN = OV, VCC WDT is not Running STOP Mode [6]
WDT is Running 1000 Mode V IN OV, V CC WDT is 7 = 5.0V 600 A 800 STOP
AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram
R//W
13 12
Port 0, /DM
16 19 3
Port 1
1
A7 - A0
2
D7 - D0 IN
9
/AS
8 4 5 6 18 11
/DS (Read)
17
10
Port1
A7 - A0
14
D7 - D0
OUT
15 7
/DS (Write)
External I/O or Memory Read/Write Timing
8
AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table
No Symbol Parameter VCC Note[3] 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 T A = 0C to +70C 8 MHz 12 MHz Min Max Min Max 55 55 70 70 400 400 80 80 0 0 300 300 165 165 260 260 0 0 85 95 60 70 70 70 70 70 80 80 70 80 475 475 100 100 115 75 55 55 65 65 115 75 35 35 0 0 45 55 30 45 45 45 45 45 55 55 45 55 310 310 100 100 115 75 55 55 55 55 0 0 200 200 110 110 150 160 0 0 85 95 60 70 70 70 70 70 80 80 70 80 475 475 65 65 115 75 35 35 35 35 45 45 250 250 80 80 0 0 300 300 165 165 260 260 0 0 45 55 30 45 45 45 45 45 55 55 45 55 310 310 T A = -40C to +105C 8 MHz 12 MHz Min Max Min Max 55 55 70 70 400 400 55 55 0 0 200 200 110 110 150 160 35 35 45 45 250 250 Units Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
TdA(AS) TdAS(A) TdAS(DR) TwAS Td TwDSR TwDSW
Address Valid to /AS Rising Delay /AS Rising to Address Float Delay /AS Rising to Read Data Required Valid /AS Low Width
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
[2] [2] [1,2] [2]
Address Float to 3.3 /DS Falling 5.0 /DS (Read) Low Width 3.3 5.0
[1,2] [1,2] [1,2] [2] [2] [2] [2] [2] [2] [2] [1,2] [2] [1,2] [2]
/DS (Write) Low Width 3.3 5.0 TdDSR(DR) /DS Falling to Read 3.3 Data Required Valid 5.0 ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay /DS Rising to /AS Falling Delay R//W Valid to /AS Rising Delay 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 0.0 5.0 3.3 5.0
/DS Rising to R//W Not Valid TdDW(DSW) Write Data Valid to /DS Falling (Write) Delay TdDS(DW) TdA(DR) TdAS(DS) TdDI(DS) TdDM(AS) /DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid /AS Rising to /DS Falling Delay Data Input Setup to /DS Rising /DM Valid to /AS Falling Delay
Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] 5.0V 0.5V, 3.3V 0.3V. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
9
AC CHARACTERISTICS Additional Timing Diagram
1 3
Clock
2 7 7 2 3
T
IN
4 6 5
IRQ
N
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Additional Timing
10
AC CHARACTERISTICS Additional Timing Table
No Symbol Notes Parameter VCC Note[6] 1 2 3 4 5 6 7 8A TpC TrC,TfC TwC TwTinL TwTinH TpTin Input Clock Period 3.3V 5.0V Clock Input Rise 3.3V and Fall Times 5.0V Input Clock Width Timer Input Low Width 3.3V 5.0V 3.3V 5.0V TA = 0C to 70C 8 MHz Min Max 125 100000 125 100000 25 25 37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC 12 5.0V 12 5TpC 5TpC 12 12 100 70 3TpC 3TpC 3TpC 3TpC 12 12 12 MHz Min Max 83 83 100000 100000 15 15 TA = -40C to 105C 8 MHz Min Max 125 100000 125 100000 25 25 37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC 12 12 3TpC 3TpC 8TpC 8TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC ns ns [7] [8] 12 MHz Min Max 83 83 100000 100000 15 15 ns ns ns ns ns ns ns ns 3TpC 3TpC 8TpC 8TpC 100 100 ns ns ns ns [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1,2] [1,2] Units
26 26 100 70
26 26 100 70
Timer Input 3.3V High Width 5.0V Timer Input Period 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V
TrTin,TfTinTimer Input Rise and Fall Timers TwIL Interrupt Request Low Time Int. Request Low Time
8B TwIL [1,3] [1,3] 9 TwIH [1,2] [1,2] 10 Twsm
Interrupt Request Input High Time
STOP Mode 3.3V Recovery Width Spec 3.3V 5.0V
11
AC CHARACTERISTICS Additional Timing Table (Continued)
No Symbol Parameter VCC Note[6] 3.3V 5.0V 3.3V 5.0V 3.3V [5] 5.0V [5] [5] [5] 3.3V [5] 5.0V [5]
Notes: [1] Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 0 [5] Reg. WDTMR [6] 5.0V 0.5V, 3.3V 0.3V [7] Reg. SMR - D5=0 [8] Reg. SMR - D5=1
T A = 0C to 70C 8 MHz 12 MHz Min Max Min Max 5TpC 5TpC 10 5 30 15 50 25 200 100 10 5 30 15 50 25 200 100 5TpC 5TpC
T A = -40C to 105C Units 8 MHz 12 MHz Min Max Min Max 5TpC 5TpC 10 5 30 15 50 25 200 100 10 5 30 15 50 25 200 100 5TpC 5TpC ms ms ms ms ms ms ms ms
Notes
11 12 [5] [5]
Tost Twdt
Oscillator Startup Time Watchdog Timer Delay Time
[4] [4] D0 = 0 D1 = 0 D0 = 1 D1 = 0 D0 = 0 D1 = 1 D0 = 1 D1 = 1
3.3V 5.0V
12
AC CHARACTERISTICS Handshake Timing Diagrams
Data In Data In Valid Next Data In Valid
1 3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
13
AC CHARACTERISTICS Handshake Timing Table
No Symbol Parameter VCC Note[1] TA = 0C To 70 C 8 MHz 12 MHz Min Max Min Max 0 0 160 115 155 110 160 115 120 80 0 0 63 63 0 0 160 115 110 80 110 80 110 80 110 80 0 0 42 42 0 0 160 115 110 80 110 80 0 0 160 115 155 110 160 115 120 80 0 0 63 63 0 0 160 115 110 80 110 80 T A = -40 C To 105 C 8 MHz 12 MHz Data Min Max Min Max Direc0 0 160 115 155 110 160 115 120 80 0 0 42 42 0 0 160 115 0 0 160 115 155 110 160 115 120 80 IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
tion 1 2 3 4 5 6 7 8 9 10 11 TsDI(DAV) ThDI(DAV) TwDAV Data In Setup Time Data In Hold Time Data Available Width 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V
TdDAVI(RDY) DAV Falling to RDY Falling Delay TdDAVId(RDY) DAV Rising to RDY Falling Delay TdDO(DAV) RDY Rising to DAV Falling Delay TcLDAV0(RDY)Data Out to DAV Falling Delay TcLDAV0(RDY)DAV Falling to RDY Falling Delay TdRDY0(DAV) RDY Falling to DAV Rising Delay TwRDY RDY Width TdRDY0d(DAV) RDY Rising to DAV Falling Delay
Note: [1] 5.0 V 0.5V, 3.3V 0.3V
(c) 1991 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 171-980 A/B ZILOG CPTO FAX 408 370-8056/8027
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